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CX_QUAD

by Qiao Ning last modified May 24, 2017 02:04 AM
four cores asynchronous spiking neural network

pic_of_CX_QUAD

by Qiao Ning last modified Dec 11, 2014 01:52 PM
pic_of_CX_QUAD
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Size: 3.0 MB

die_photo of CX_QUAD

by Qiao Ning last modified Dec 11, 2014 01:55 PM
die_photo of CX_QUAD
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Size: 1.4 MB

Description

by Qiao Ning last modified May 24, 2017 02:05 AM
CX_QUAD is a four-core asynchronous mixed-signal spiking neural network chip fabricated in 180nm process with 1k IF neurons per chip, 64 digital synapses (CAM) per neuron, 3-level hierarchical on-chip routers for local core, core-to-core and chip-to-chip communications. Benefit from novel architecture of core and fast asynchronous hierarchical routers, CX_QUAD can support at least 4x4 chips directly events communication (all-to-all connections) to build larger low latency event-based spiking neural network. With standard 4 phase handshaking, CX_QUAD is also suitable to interface directly to spiking sensor for recognition tasks. CX_QUAD is a memory-optimized system (1/4 memories comparing with cross-bar structure) with large fan-out (16 x 256) and has capacity to realize massive connections neural networks.


features:

  • four-core chip with 1k adaptive IF neurons per chip and 64 CAM-words per neuron
  • on-chip BiasGens to supply 25 biases for each core
  • 3-level hierarchical routers for local core, core-to-core, chip-to-chip communications
  • scalable architecture, can realize 16 chips, 16k neuorns event-based spiking computing network
  • input-interface with 4-bit chip ID to P2P program and configure any chip on board
  • 4 different synapse types can be chosen for each synapse
  • fine tune parameters of analog neuron and DPI circuits by analog biases
  • independent suspend operation for each core and fast operation (<10ns) for changing one CAM/SRAM word contents for off-chip learning.

 

Technology: AMS 0.18u CMOS 6M
Size:        43.79 mm2 (5301.24um x 8261.24umm)
Voltage: 1.8V for core, 1.8-5V for padframe
PADs number: 240
Package:       
Pin Information:  Padframe
Bonding Diagram: 

 

Buses on four directions:

addr<19:12>, source_core_id<11:10>, sign_y<9>,dy<8:7>,sign_x<6>,dx<5:4>,core_id<3:0>

Architecture

by Qiao Ning last modified Aug 28, 2014 11:29 AM
Architecture
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input interface

by Qiao Ning last modified May 24, 2017 02:05 AM
One interface between chips and FPGAs or chips and spiking sensors.
 input_interface of the CX_QUAD supports the following operations:
  • Program CAM/SRAM according to chip_id to each chip (WENxASI) for initial programming whole chip or suspend any core (bit<17>) for suspending and fast programming specific CAM/SRAM words.
  • Program BiasGen to fine tune 25 parameters per core, 100 parameters per chip.
  • Send events to specific destination chips directly using Chip_id or send events through chips to chip using dx and dy.
  • set time constants tau tau1/tua2 of neurons by core, set specific neurons to tau2 according to configuring address
  • monitor one neuron's membrane potential in one core, 4 neurons in one chips can be monitored at the same time

input interface_decoder

by Qiao Ning last modified Dec 14, 2015 05:37 PM
input interface_decoder
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IFMC_Design_Interim_Report.pdf

by Qiao Ning last modified Aug 25, 2014 03:42 PM
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! Notice!!! Some descriptions in this file are old and may be not the real ideas and architectures used in CX_QUAD!!!!!!!!!!! !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

IFMC_Design_Interim_Report.pdf — PDF document, 2246 kB (2300069 bytes)

Bonding diagram

by Qiao Ning last modified Oct 02, 2014 01:33 PM
CQFP 240 was chosen for packaging CX_QUAD.

CX_QUAD_bonding_diagram.pdf — PDF document, 1984 kB (2031855 bytes)

Pins information

by Qiao Ning last modified Oct 02, 2014 01:40 PM
pin information of CX_QUAD

Bonding_diagram_CX_QUAD.ods — ODS spreadsheet, 19 kB (19586 bytes)