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BiasGen_x64

by Qiao Ning last modified Mar 16, 2017 11:29 AM
Addressable (64 branches )and programmable Bias Generator for MN256R1

Circuit Description

Programmable and addressable bias current reference circuits. 15 configuration bits of each bias are used to program the coarse-fine current selection and the voltage buffer.

3bits are allocated for coarse current selection.

8bits for fine current selection.

4bits for buffer configuration.

Pins and control signals

BitIn:   Data input for programming address, parameters for programming, and monitor address.

CLK:    Clock signal for programming

nLatch: 

AddrSel:

MonitorSel:

Monitor_EN:  Current monitor enable signal. When “1”  the chosen bias  will be monitored.

rx: will go to pad to connect R to ground off-chip

PowerDown: High enable signal (Powerdown when "1")

PDrain: For monitoring the Pbias current for the chosen bias off-chip.

NDrain: For monitoring the Pbias current for the chosen bias off-chip.

Bias<0:63>: 64 separated programmable bias branches.

SSN: Improve source potential for copying small current( <1nA).

SSP: Improve source potential for copying small current( <1nA).

masterBiasN: go to pad for stability.

 

Programming bits for BiasBranch:

IBIT<12> IBIT<13> IBIT<14>
Bias Voltage
Coarse Current
Simulated(R=10k)
000
BiasCB0 64I 24u
001 BiasCB1 8I 3.2u
010 BiasCB2 I 0.4u
011 BiasCB3 I/8 50n
100 BiasCB4 I/64 6.5n
101 BiasCB5 I/8^3 820p
110 BiasCB6 I/8^4 105p
111 BiasCB7 I/8^5 15p

           IBIT/Value             
                “0”               
   “1”  
IBIT<11> 0 Icoarse/2
IBIT<10> 0 Icoarse/4
IBIT<9> 0 Icoarse/8
IBIT<8> 0 Icoarse/2^4
IBIT<7> 0 Icoarse/2^5
IBIT<6> 0 Icoarse/2^6
IBIT<5> 0 Icoarse/2^7
IBIT<4> 0                    Icoarse/2^8                   

 

            IBIT/Value           
   “0”  
   “1”  
IBIT<3> LowBias
     HighBias (without SSN, SSP)    
IBIT<2>         CascodeBias        
Normal
IBIT<1> PBias
NBias
IBIT<0>
BiasDisable
BiasEnable

 

If IBIT<2>=1 for Nbias Normal=1 , cascodeBias=0 cascode for Nbias will not be enabled.

If IBIT<2>=0 Cascode=1, Cascode for NBias will be enabled.

If IBIT<2>=1 for Pbias Normal=1 , cascodeBias=0 cascode for Pbias will not be enabled.

If IBIT<2>=0 Cascode=1, Cascode for PBias will be enabled.

-----------------------------------------------------------------------------------------------------------------------

for Nbias if IBIT<3>=1 Lowbias=0 Source of NMOS will be connected to gnd

for Pbias when coarse current smaller than 101 (1/8^3) NPart auto SSN

IBIT<3>=1 means source of PMOS will be connected to vdd

IBIT<3>=0 means source of PMOS will be connected to SSP

-----------------------------------------------------------------------------------------------------------------------

IBIT<1>=1 NBias Enabled

IBIT<1>=0 PBias Enabled

example:

 

IBIT<14:12>=000 means coarse current 000 (Icoarse=24u) is chosen 

IBIT<11:4>=10100001 means  Ibias = Icoarse/2 + Icoarse/8 + Icoarse/2^8

IBIT<3:0>=1111 means normal bias voltage NBias without SSN with the current Ibias will be generated.


Simulation Results

 

8 coarse currents with scanned fine code (8-bit). Without SSN and SSP, current smaller than 1pA can not be generated.

Scaned_NBias_Current

 

Small coarse currents (<1nA) with scanned fine code (8-bit)using SSN and SSP. Small current ( the smallest current might be 50fA according to simulation)  can be obtained.

Nbias_with_SSN

Application

BiasBranch Bias Name in circuit
NBias/PBias Current Range
Description
BiasBranch<0> 
IF_RST_N!
     
BiasBranch<1>
IF_BUF_P!
     
BiasBranch<2>
IF_AHTHR_N!
     
 BiasBranch<3>
IF_RFR1_N!
     
BiasBranch<4>
IF_RFR2_N!
     
BiasBranch<5>
IF_AHW_P!
     
BiasBranch<6>
IF_AHTAU_N!
     
 BiasBranch<7>
IF_DC_P!
     
BiasBranch<8>
IF_TAU2_N!
     
 BiasBranch<9>
IF_TAU1_N!
     
 BiasBranch<10>
IF_NMDA_N!
     
 BiasBranch<11>
IF_CASC_N!
     
BiasBranch<12>
IF_THR_N!
     
 BiasBranch<13>
SL_THDN_P!
     
 BiasBranch<14>
SL_MEMTHR_N!
     
 BiasBranch<15>
SL_BUF_N!
     
 BiasBranch<16>
SL_THMIN_N!
     
BiasBranch<17>
SL_WTA_P!
     
 BiasBranch<18>
SL_CATHR_P!
     
 BiasBranch<19>
SL_THUP_P!
     
BiasBranch<20>
SL_CATAU_P!
     
 BiasBranch<21>
SL_CAW_N!
     
 BiasBranch<22>
VA_INH_P!
     
 BiasBranch<23>
VDPII_TAU_N!
     
 BiasBranch<24>
VDPII_THR_N!
     
 BiasBranch<25>
VA_EXC_N!
     
 BiasBranch<26>
VDPIE_TAU_P!
     
 BiasBranch<27>
VDPIE_THR_P!
     
 BiasBranch<28>
FB_REF_P!
     
 BiasBranch<29>
FB_WTA_N!
     
 BiasBranch<30>
FB_BUF_P!
     
BiasBranch<31>
FB_CASC_N!
     
BiasBranch<32>
FB_INVERSE_TAIL_N!
     
BiasBranch<33>
FB_INVERSE_REF_N!
     
BiasBranch<34>
PDPI_BUF_N!
     
BiasBranch<35>
PDPI_VMONPU_P!
     
BiasBranch<36>
PDPI_TAU_P!
     
BiasBranch<37>
PDPI_THR_P!
     
BiasBranch<38>
NPDPIE_THR_P!
     
BiasBranch<39>
NPDPIE_TAU_P!
     
BiasBranch<40>
NPDPII_TAU_P!
     
BiasBranch<41>
NPDPII_THR_P!
     
BiasBranch<42>
NPA_WEIGHT_STD_N!
     
BiasBranch<43>
NPA_WEIGHT_INH0_N!
     
BiasBranch<44>
NPA_PWLK_P!
     
BiasBranch<45>
NPA_WEIGHT_INH1_N!
     
BiasBranch<46>
NPA_WEIGHT_EXC_P!
     
BiasBranch<47>
NPA_WEIGHT_EXC1_P!
     
BiasBranch<48>
NPA_WEIGHT_EXC0_P!
     
BiasBranch<49>
NPA_WEIGHT_INH_N!
     
BiasBranch<50>
PA_WDRIFTDN_N!
     
BiasBranch<51>
PA_WDRIFTUP_P!
     
BiasBranch<52>
PA_DELTAUP_P!
     
BiasBranch<53>
PA_DELTADN_N!
     
BiasBranch<54>
PA_WHIDN_N!
     
BiasBranch<55>
PA_WTHR_P!
     
BiasBranch<56>
PA_WDRIFT_P!
     
BiasBranch<57>
PA_PWLK_P!