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Development of neuromorphic VLSI devices

by Federico Corradi — last modified Nov 28, 2012 12:26 AM


Development of neuromorphic VLSI devices.

We are currently developing CMOS circuitry for VLSI low-power implementation of biophysically realistic and scalable neural circuits. In our neuromophic chips we explore the space between digital and analog circuit design, focusing on power saving within stability constraints.

The neuromorphic devices that we are currently developing are going to be fabricated in AMS 0.18um technology. Figure 1 shows a picture of the complete layout of our first test chip that has been sent to fabrication in September 2012. It comprises four main modules: (i) digital memory, (ii) analog-learning synaptic matrix (iii) neurons arrays and (iv) digital communication infrastructure (Address-Event-Representation).

The digital memory serves as  'virtual synapses' and it store synaptic weights with 4 bit precision. Digital weights are then translated in analog currents that are sent to the on chip analog synapses which then produce post-synaptic discharges capable of emulating a response to pre-synaptic action potentials.
The synaptic matrix enable reconfigurable on chip connections and allow us to program the chip with 'ad hoc' connectivity matrix. This biologically inspired synapse contains circuitry that implements a stochastic learning algorithm first introduced by Fusi [Fusi04] which has already been highly effective in learning to classify complex stimuli [Neuromorphic classifiers]

The neuron core array is an instantiation of the low-power Differential-Pair Integrator neuron circuit developed during the past decade by G. Indiveri. It has in fact many biologically plausible features as spike-frequency adaptation, refractory period and leak. It is also capable of reproducing many interesting dynamical behaviours observed in its biological counterpart as regular spiking, tonic firing, bursting, frequency adaptation as well as spontaneous activity.  The digital AER communication block allow us to have a distributed network interconnected in a multi-chip system capable of receiving input and/or controlling others neuromorphic sensory devices (retina,coclea).


SpikeBetter - test chip 0.18u

 Figure 1 test chip 2.8x2.5um in AMS 0.18 um technology. 1) Digital Synapses is made of an asynchronous SRAM used as virtual synapses. The main core of the chip is made of an 2) analog implementation of learning synapses which implements a biologically plausible stochastic learning rule first introduced by Fusi [Fusi2002].  3) The neuron array consists of 64 neurons 4)  Communication with other neuromorphic devices or with standard computer is made via digital AER communication standard.